In an impromptu pre-IDF press briefing today, Intel disclosed a wealth of new information regarding its roadmap product efforts, upcoming multi-core processors and their associated platforms. The discussion, chaired by the Senior VP of Intel's Digital Enterprise Group, Pat Gelsinger, even covered additional detail of the company's future play in the discrete GPU space, code-named Larrabee.
Pat dove in quickly with what was probably Intel's most ambitious design effort yet, that will bear fruit some time in 2H '08, the new six-core infused Dunnington server/workstation processor.Some of the more interesting take-aways with Dunnignton were that Intel has re-tooled a shared L2/L3 cache architecture and that Dunnington will in fact be socket compatible with their current Caneland platform. However, we would expect that actual drop-in compatibility is guaranteed only by system board manufacturers with capable power circuits and up to date BIOS microcodes. Pat also stressed that Dunnington, though comprised of some 1.9 billion transistors and 16MB of L3 cache, will adhere to Intel's current power efficiency characteristics of their advanced 45nm Hi-K processing technology. Several systems were referenced in a recent third-party SPECpower Energy Efficiency test, showing Intel's current leadership with the Xeon 5400 and 5300 series of products in the top ten slots currently in the industry.Next, Gelsinger stepped up with Intel's mainstream big gun, the company's forthcoming Nehalem quad core processor. Nehalem is slated to be Intel's first mainstream desktop product with a direct-attached serial interface, dubbed QPI or QuickPath Interconnect, a monumental upgrade over their now seriously aging Front Side Bus architecture.Easily one the most interesting and talked-about aspects of Nehalem, Intel's new QuickPath Interconnect will provide for high speed, low latency transactions coming on and going off chip. Previously, one way Intel was able to mitigate FSB latency and bus turn-around times, was with larger amounts of L2 cache that provided more on-chip memory resources and thus required fewer requests over the FSB and out to system memory. Nehalem however, will have only 256K of L2 cache per core and a 8MB of L3 cache per chip. Comparatively, AMD's future 45nm quad core Phenoms will have 512K of L2 cache per core and 6MB of L3 total. Obviously Intel knows their architecture best but clearly this cache architecture seems a bit spartan versus previous Intel architectures, though admittedly exorbitant amounts of on-chip cache should no longer be a requirement with the new QPI interface at Nehalem's disposal.Easily one the most interesting and talked-about aspects of Nehalem, Intel's new QuickPath Interconnect will provide for high speed, low latency transactions coming on and going off chip. Previously, one way Intel was able to mitigate FSB latency and bus turn-around times, was with larger amounts of L2 cache that provided more on-chip memory resources and thus required fewer requests over the FSB and out to system memory.
Nehalem however, will have only 256K of L2 cache per core and a 8MB of L3 cache per chip. Comparatively, AMD's future 45nm quad core Phenoms will have 512K of L2 cache per core and 6MB of L3 total. Obviously Intel knows their architecture best but clearly this cache architecture seems a bit spartan versus previous Intel architectures, though admittedly exorbitant amounts of on-chip cache should no longer be a requirement with the new QPI interface at Nehalem's disposal.
Pat dove in quickly with what was probably Intel's most ambitious design effort yet, that will bear fruit some time in 2H '08, the new six-core infused Dunnington server/workstation processor.Some of the more interesting take-aways with Dunnignton were that Intel has re-tooled a shared L2/L3 cache architecture and that Dunnington will in fact be socket compatible with their current Caneland platform. However, we would expect that actual drop-in compatibility is guaranteed only by system board manufacturers with capable power circuits and up to date BIOS microcodes. Pat also stressed that Dunnington, though comprised of some 1.9 billion transistors and 16MB of L3 cache, will adhere to Intel's current power efficiency characteristics of their advanced 45nm Hi-K processing technology. Several systems were referenced in a recent third-party SPECpower Energy Efficiency test, showing Intel's current leadership with the Xeon 5400 and 5300 series of products in the top ten slots currently in the industry.Next, Gelsinger stepped up with Intel's mainstream big gun, the company's forthcoming Nehalem quad core processor. Nehalem is slated to be Intel's first mainstream desktop product with a direct-attached serial interface, dubbed QPI or QuickPath Interconnect, a monumental upgrade over their now seriously aging Front Side Bus architecture.Easily one the most interesting and talked-about aspects of Nehalem, Intel's new QuickPath Interconnect will provide for high speed, low latency transactions coming on and going off chip. Previously, one way Intel was able to mitigate FSB latency and bus turn-around times, was with larger amounts of L2 cache that provided more on-chip memory resources and thus required fewer requests over the FSB and out to system memory. Nehalem however, will have only 256K of L2 cache per core and a 8MB of L3 cache per chip. Comparatively, AMD's future 45nm quad core Phenoms will have 512K of L2 cache per core and 6MB of L3 total. Obviously Intel knows their architecture best but clearly this cache architecture seems a bit spartan versus previous Intel architectures, though admittedly exorbitant amounts of on-chip cache should no longer be a requirement with the new QPI interface at Nehalem's disposal.Easily one the most interesting and talked-about aspects of Nehalem, Intel's new QuickPath Interconnect will provide for high speed, low latency transactions coming on and going off chip. Previously, one way Intel was able to mitigate FSB latency and bus turn-around times, was with larger amounts of L2 cache that provided more on-chip memory resources and thus required fewer requests over the FSB and out to system memory.
Nehalem however, will have only 256K of L2 cache per core and a 8MB of L3 cache per chip. Comparatively, AMD's future 45nm quad core Phenoms will have 512K of L2 cache per core and 6MB of L3 total. Obviously Intel knows their architecture best but clearly this cache architecture seems a bit spartan versus previous Intel architectures, though admittedly exorbitant amounts of on-chip cache should no longer be a requirement with the new QPI interface at Nehalem's disposal.
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